In HKMG gate first technologies, the final metal gate topology, particularly, the thickness of a negative channel field effect transistor (nMOS) work function metal stack and of a positive channel field effect transistor (pMOS) work function metal stack are critical for gate etching and manufacturing. However, nMOS and pMOS workfunction thickness is difficult to control through various fabrication processes. A final metal gate topology is conventionally formed by forming an n-type area and a p-type area in a substrate, forming a pMOS workfunction metal stack layer over both areas, removing the pMOS work workfunction metal stack over the p-type area, and forming an nMOS workfunction metal stack layer over both areas. The resulting nMOS and pMOS gates have different thicknesses, which is unsuitable for gate etching and manufacturing.
Efforts have been made to flatten the final metal stack topology by removing the nMOS and pMOS workfunction metal stacks after a drive in anneal and depositing a final metal stack without workfunction metals. However, the process delivers less workfunction setting, resulting in an inferior final metal gate.
A need therefore exists for methodology enabling formation of a final metal stack including workfunction metals with a topology suitable for gate etching and manufacturing.